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华为

Mixed-Signal Layout Engineer (Senior)

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  • 我要分享
  • 24万-48万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: Competitive salary with generous stock options,Commensurate with experience/skill

发布时间: 2017-11-01发布

职位描述

Job description:
- Individual will work closely with design engineers in the layout, physical design and verification of analog and mixed signal ICs.

Qualifications:
- 2+ years experience with Cadence Virtuoso, Mentor Calibre, Synopsys.
- DRC, LVS, Metal Fill, Tapeouts, Metal Rules, Electromigration, Fringe Cap, Via rules, Matching, Inductance noise, wire resistance.
- Basic understanding of IC design (RLC circuits and Kirchoff’s Law, symmetry, frequency response, transistor matching).
- Desired: Analog layout design (differential symmetry; ground shielding; high-frequency impedances; transistor parasitics).

职位发布者

7天

简历处理用时

100%

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